Hardware kit #20

New issue

Open

opened 2026-04-02 13:16:17 +00:00 by bcox · 0 comments

bcox commented

2026-04-02 13:16:17 +00:00

Owner

SBC7 Hardware Kit — High-Level Design

Board 1: Main Board (FPGA + Memory)

The heart of the system. Contains:

FPGA — Intel MAX 10 (10M08 or similar) or Lattice iCE40 HX. Holds the entire SBC7 SoC: CPU, RAM, ROM, VGA controller, dual UART, timers, interrupt priority logic, and clock divider. Needs a 25 MHz crystal oscillator as the system clock.
Configuration flash — On-board or FPGA-internal (MAX 10 has internal flash; iCE40 needs an external SPI flash for bitstream).
Power regulation — 5V barrel jack input, 3.3V and 1.2V regulators for the FPGA core and I/O banks.
Active-low reset circuit — RC power-on reset plus a front-panel reset button input (active-low, directly to rst_n).

Board 2: I/O Board (or section of main board)

Handles level shifting and connectors:

VGA output — A resistor-DAC on the vga_color[6:0] lines (2 bits R, 3 bits G, 2 bits B) plus direct vga_hsync/vga_vsync to a DE-15 (HD15) VGA connector. Seven resistors and a connector — very simple.
Dual RS-232 ports — Two MAX3232 (or SP3232) level shifters converting the FPGA's 3.3V TTL uart0_txd/rxd and uart1_txd/rxd to RS-232 levels. Each drives a DB-9 (DE-9) connector wired as DCE (pin 2 = TX out, pin 3 = RX in) or DTE, your choice. Only TX/RX/GND needed — no hardware flow control in the current UART design.
Programmer's switch — Active-low momentary pushbutton to prog_sw_n, directly on the front panel. Already has a metastability synchronizer and falling-edge detector in the RTL, so just a button with a pull-up resistor.
Reset button — Momentary pushbutton pulling rst_n low, with a small debounce cap.
Power switch — Simple SPST toggle on the 5V input rail.

External Interrupt Header (optional)

The top-level exposes int_n and int_vec[2:0] for an external interrupt controller. A pin header could break these out for expansion. If unused, int_n is tied high and int_vec to 3'b000 as the RTL comments specify.

DMA / Programming Header

The ext_we, ext_addr[13:0], and ext_din[6:0] signals allow loading programs into RAM while the CPU is held in reset. This could be exposed as:

A pin header for a JTAG-style programmer, or
A small microcontroller (ATtiny/RP2040) that accepts programs over USB and bitbangs them into RAM via the DMA port on power-up.

This is how you'd load user programs without burning a new ROM.

Clock Domain Summary

One clock domain: 25 MHz oscillator feeds the FPGA. The Bresenham divider inside clkdiv.sv generates a 14 MHz clock-enable for the CPU. VGA pixel timing, UARTs, and timers all run at the full 25 MHz. No external PLLs or clock distribution needed.

Signal Summary (FPGA pin count)

Signal Group	Pins
VGA (R2, G3, B2, hsync, vsync, DE)	8
UART0 (TX, RX)	2
UART1 (TX, RX)	2
Programmer's switch	1
Reset	1
External interrupt (int_n + vec)	4
DMA port (we + addr14 + data7)	22
Crystal oscillator	1
Total	~41

Well within even a 48-pin QFP FPGA package. A MAX 10 10M08SAE144 (144-pin) would leave plenty of room for expansion.

What You Don't Need

External SRAM/ROM — The FPGA block RAM handles all 16 KB of RAM and 2 KB of ROM internally.
Clock generator ICs — One 25 MHz can, everything else is internal.
Interrupt controller IC — Priority logic is in the RTL.
Flow control circuitry — UARTs are TX/RX only.

RC2014 Comparison

The RC2014 has a backplane bus with separate CPU, RAM, ROM, serial, and clock cards. The SBC7 kit would be much simpler — the FPGA absorbs everything the RC2014 spreads across 5+ cards. Your BOM is essentially: FPGA, crystal, voltage regulators, two MAX3232s, a handful of resistors for the VGA DAC, three buttons, a power switch, and connectors.

## SBC7 Hardware Kit — High-Level Design ### Board 1: Main Board (FPGA + Memory) The heart of the system. Contains: - **FPGA** — Intel MAX 10 (10M08 or similar) or Lattice iCE40 HX. Holds the entire SBC7 SoC: CPU, RAM, ROM, VGA controller, dual UART, timers, interrupt priority logic, and clock divider. Needs a 25 MHz crystal oscillator as the system clock. - **Configuration flash** — On-board or FPGA-internal (MAX 10 has internal flash; iCE40 needs an external SPI flash for bitstream). - **Power regulation** — 5V barrel jack input, 3.3V and 1.2V regulators for the FPGA core and I/O banks. - **Active-low reset circuit** — RC power-on reset plus a front-panel reset button input (active-low, directly to `rst_n`). ### Board 2: I/O Board (or section of main board) Handles level shifting and connectors: - **VGA output** — A resistor-DAC on the `vga_color[6:0]` lines (2 bits R, 3 bits G, 2 bits B) plus direct `vga_hsync`/`vga_vsync` to a DE-15 (HD15) VGA connector. Seven resistors and a connector — very simple. - **Dual RS-232 ports** — Two MAX3232 (or SP3232) level shifters converting the FPGA's 3.3V TTL `uart0_txd/rxd` and `uart1_txd/rxd` to RS-232 levels. Each drives a DB-9 (DE-9) connector wired as DCE (pin 2 = TX out, pin 3 = RX in) or DTE, your choice. Only TX/RX/GND needed — no hardware flow control in the current UART design. - **Programmer's switch** — Active-low momentary pushbutton to `prog_sw_n`, directly on the front panel. Already has a metastability synchronizer and falling-edge detector in the RTL, so just a button with a pull-up resistor. - **Reset button** — Momentary pushbutton pulling `rst_n` low, with a small debounce cap. - **Power switch** — Simple SPST toggle on the 5V input rail. ### External Interrupt Header (optional) The top-level exposes `int_n` and `int_vec[2:0]` for an external interrupt controller. A pin header could break these out for expansion. If unused, `int_n` is tied high and `int_vec` to `3'b000` as the RTL comments specify. ### DMA / Programming Header The `ext_we`, `ext_addr[13:0]`, and `ext_din[6:0]` signals allow loading programs into RAM while the CPU is held in reset. This could be exposed as: - A pin header for a JTAG-style programmer, or - A small microcontroller (ATtiny/RP2040) that accepts programs over USB and bitbangs them into RAM via the DMA port on power-up. This is how you'd load user programs without burning a new ROM. ### Clock Domain Summary One clock domain: 25 MHz oscillator feeds the FPGA. The Bresenham divider inside `clkdiv.sv` generates a 14 MHz clock-enable for the CPU. VGA pixel timing, UARTs, and timers all run at the full 25 MHz. No external PLLs or clock distribution needed. ### Signal Summary (FPGA pin count) | Signal Group | Pins | |---|---| | VGA (R2, G3, B2, hsync, vsync, DE) | 8 | | UART0 (TX, RX) | 2 | | UART1 (TX, RX) | 2 | | Programmer's switch | 1 | | Reset | 1 | | External interrupt (int_n + vec) | 4 | | DMA port (we + addr14 + data7) | 22 | | Crystal oscillator | 1 | | **Total** | **~41** | Well within even a 48-pin QFP FPGA package. A MAX 10 10M08SAE144 (144-pin) would leave plenty of room for expansion. ### What You Don't Need - **External SRAM/ROM** — The FPGA block RAM handles all 16 KB of RAM and 2 KB of ROM internally. - **Clock generator ICs** — One 25 MHz can, everything else is internal. - **Interrupt controller IC** — Priority logic is in the RTL. - **Flow control circuitry** — UARTs are TX/RX only. ### RC2014 Comparison The RC2014 has a backplane bus with separate CPU, RAM, ROM, serial, and clock cards. The SBC7 kit would be much simpler — the FPGA absorbs everything the RC2014 spreads across 5+ cards. Your BOM is essentially: FPGA, crystal, voltage regulators, two MAX3232s, a handful of resistors for the VGA DAC, three buttons, a power switch, and connectors.

No labels

No milestone

No project

No assignees

1 participant

Notifications

Due date

The due date is invalid or out of range. Please use the format "yyyy-mm-dd".

No due date set.

Dependencies

No dependencies set.

Reference

bcox/sbc7#20

No description provided.

Rows
Columns